For some, there are times when one knows how a logic function is supposed to work but forgets how to code it in Verilog even though one has done it countless times in many projects. Here is one such function that tends to be taken for granted:
Checking 8-bit (byte) data protected with even-parity.
Using Verilog, parity checking can be coded with the help of the ”^” character. It is a symbol for an Exclusive-OR logic gate. Exclusive-OR essentially means if two bits are different, then generate a 1, if they are the same generate a 0. It is great at finding out whether there are an odd or even number of bits on a bus. In this article, I won’t go into much detail about what parity is used for since it is probably much easier to use a search engine to get the 411 about it. Instead, I’ll just provide a couple of code snippets that can be used as a template in your own modules.
In this example, data is contained in data[7:0] and is protected by even-parity. parity contains the expected parity bit and is compared against an Exclusive-OR of all the data bits(data[7:0]). If the Exclusive-OR of data bits equals the expected value, then no error was detected. Otherwise, an error is detected.
always @(*) begin if (^data[7:0] == parity) begin parity_error = 1'b0; end else begin parity_error = 1'b1; // parity error detected end end
Snippet 2: For a bus that is composed of many bytes and uses even-byte parity, Verilog code could look something like this:
always @(*) begin if ( (^data[7:0] == parity) & (^data[15:8] == parity) & (^data[23:16] == parity) & (^data[31:24] == parity) ) begin parity_error = 1'b0; // no error detected end else begin parity_error = 1'b1; // parity error detected end end
Caveat Please note that there is a rare possibility that a data error has occurred but is not detected. This event could happen if data[7:0] or parity is altered in such a way that their comparison will equal. For instance, say data[7:0] originally contained 01101110 and parity contained 1. However, if during data[7:0]'s transit from one logic circuit to another and data[7:0] was corrupted and ended up becoming 10011110, the parity checker won't detect that such an error occurred. This is because the checker only verifies whether an even or odd number of 1 bits are on the data bus. Are there other Verilog code examples you'd like to see? Feel free to send me a note...