I don’t work on this area of chip design but thought this information would be helpful in understanding things during the physical implementation phase of design. This information was originally sourced from ASICDESIGN@yahoogroups.com.
Decap cap cells are nothing but capacitors placed between VDD-VSS . These are placed to overcome dynamic I.R drop . Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch. Due to this simultaneous switching a high current is drawn from the power grid (for a very small duration). If the source of power is very far from a flop seeing dynamic I.R. drop, metastability issues can crop in.
To overcome this decaps are added. At an active edge of clock when the currrent requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current .
Decaps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.
hope this helps.:Nikhil
